Samsung debuts three next-generation memory technologies for AI data centers — zHBM, zNAND-O, and BV-NAND all rely on advanced wafer bonding technologies
This week, Samsung presented its vision for next-generation memory and storage solutions both for AI and general-purpose applications at the Future of Memory and Storage (FMS) 2026 conference. The company introduced zHBM, zNAND-O, and BV-NAND technologies at the event, and while they are aimed at very different applications, they share one common ingredient: they all rely on wafer bonding.
Here’s a breakdown of each type of technology that the company announced.
- zHBM: Samsung’s vision for custom HBM ultra-high-performance memory that will sit on top of logic dies.
- zNAND-O: NAND memory that can be bonded atop a logic device to maximize bandwidth, reduce latency, and minimize power consumption.
- BV-NAND (aka Samsung’s 10th Generation V-NAND): Samsung’s take on bonding NAND arrays atop all the circuitry needed to operate them. This is essentially next-generation 3D NAND technology that is used today by almost everyone, including Kioxia/Sandisk, SK Hynix, and YMTC (which was the first company to adopt such a method).
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zHBM: Placing HBM stack on top of logic
Around the time we first heard about HBM4’s 2,048-bit interface, we read a ‘semi-official’ report that SK hynix and its partners were considering vertical integration of HBM4 stacks on top of logic chips. To a large degree, companies were considering installing these memory stacks on top of their processors as they doubted that it would be possible and feasible to use interposers to connect HBM4 stacks to AI accelerators. Over time, it turned out that integration of memory on top of logic is complicated when it comes to cooling, power delivery, and developing interposers that can handle a 2,048-bit memory interface. Samsung’s zHBM appears to be a continuation of that effort.
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Samsung’s zHBM concept places HBM directly on top of an AI accelerator instead of on its perimeter, which greatly reduces the distance data must travel between compute and memory. The company says this architecture can increase bandwidth and power efficiency and projects that it can provide 8x the ‘performance of HBM5‘, while its advanced wafer bonding is expected to enable over 10x higher memory density, 3x better energy efficiency, and more than 50% lower thermal resistance than HBM5.
While Samsung’s claims about the zHBM look incredibly impressive, they are vague. For example, when the company claims that a ‘next-generation interface system incorporating zHBM’ will deliver ‘approximately eight times the performance of HBM5,’ it never explicitly states whether this refers to memory bandwidth, actual application performance due to a combination of improvements over standard HBM, or something else. Had Samsung intended to compare raw bandwidth, it would likely have used more precise wording, such as ‘8x higher bandwidth.’
Instead, the general term ‘performance’ may have many meanings. The same applies to references of improved power efficiency, higher memory density, and lower thermal resistance compared to HBM5, a standard that has not been fully defined or ratified. To make matters even more imprecise, Samsung mentions thermal resistance, which depends on implementation rather than the standard. Finally, Samsung didn’t reveal which die stacking/bonding technology it will use for zHBM.
In any case, Samsung says that zHBM will also support customer-specific designs and will enable custom IP to be integrated into the interconnect layer (which plays a role similar to the base die, though it is definitely not a base die per se) between the HBM stack and the AI processor, which essentially means that zHBM is not necessarily an industry-standard solution, so it might be implemented with additional perks.
For now, Samsung hasn’t disclosed any timeframes for when it plans to offer its zHBM solutions. The only clue is that it compares it to HBM5, which is likely to see the light of day sometime in the late 2020s or early 2030s.
zNAND-O(on-device): Put storage close to compute
Samsung also unveiled zNAND-O, a high-performance NAND memory currently in development that will enable putting four or eight stacks of NAND devices on top of logic dies. zNAND-O(n) device is based on the company’s V-NAND platform (or rather, BV-NAND) and is meant to combine high storage density with improved I/O performance and low latency.
Samsung claims that the tech is suitable for edge AI systems running real-time, data-intensive inference workloads, though, of course, there are many other applications that can benefit from high-performance on-package storage.
Since the technology is in development, Samsung hasn’t shared much information about it, even keeping the schematics of how it plans to put zNAND-O layers on top of a logic under wraps. We can speculate that since Samsung mentions ‘improved I/O performance and low-latency,’ it may be planning to exploit both the inherently parallel architecture of NAND memory with a high-performance interface, though we will not try to dive into details for the sake of not making the discussion too speculative.
BV-NAND: Good old V-NAND gets a new treatment
With BV-NAND, Samsung is essentially introducing a new brand name for its next-generation 3D NAND that bonds the NAND array on top of the I/O and logic wafer. This, in turn, produces the layer itself using high-performance logic process technologies and enables higher I/O speeds.
Samsung formally announced its 400-layer-class V-NAND (aka 10th Generation V-NAND) some time ago, and even disclosed that its areal density would be 28 Gb/mm2 with a maximum I/O speed reaching 5600 MT/s. This likely stipulates the usage of a pinout that is different from the 3D NAND packages used today. While the areal density of Samsung’s 10th Gen TLC V-NAND is slightly lower when compared to that of Kioxia/Sandisk’s BiCS10 TLC NAND, its maximum I/O speed is significantly higher, which perhaps justifies the new branding.
| Header Cell – Column 0 |
Samsung |
Samsung |
Sandisk/Kioxia |
Sandisk/Kioxia |
Kioxia/Sandisk |
Micron |
SK hynix |
YMTC |
YMTC |
|---|---|---|---|---|---|---|---|---|---|
|
Generation |
V10 |
V9 |
BiCS10 |
BiCS10 |
BiCS 8 |
Gen 9 (G9) |
Gen 9 |
? |
Xtacking 3.0/Gen 4 |
|
Layers |
4xx-Layer |
290-Layer (?) |
332-Layer |
332-Layer |
218-Layer |
276-Layer |
321-Layer |
232-Layer |
232-Layer |
|
Density |
28 Gb mm^2 |
17 Gb mm^2 |
>37 Gb/mm^2 |
>29 Gb/mm^2 |
22.9 Gb mm^2 (?) |
21.0 Gb mm^2 |
20 mm^2 |
>20 Gb mm^2 |
19.8 Gb mm^2 |
|
Architecture |
TLC |
TLC |
QLC |
TLC |
QLC |
TLC |
TLC |
TLC |
QLC |
|
Die Capacity |
1 Tb |
1 Tb |
? |
1 Tb |
2 Tb |
1 Tb |
1 Tb |
1 Tb |
1 Tb |
|
I/O Speed |
Up to 5600 MT/s |
Up to 3200 MT/s |
Up to 4800 MT/s |
Up to 4800 MT/s |
Up to 3600 MT/s |
Up to 3600 MT/s |
? |
? |
? |
Considering the fact that Samsung rarely sells its memory to third parties and prefers to market client SSDs itself, a new brand for memory can be a sales driver, even if actual high-end drive performance is limited by a PCIe 5.0 x4 interface rather than by 3D NAND memory I/O. Then again, the performance of mid-range PCIe Gen5 SSDs that rely on a quad-channel NAND controller depends on 3D NAND I/O today, so marketing them under a new flash memory brand is a certain way to attract attention and then sell decent performance.
Samsung’s new brand strategy
As the new name of the FMS tradeshow implies, the announcements touch upon very distinct industry needs. In the case of Samsung, we are talking about high-performance data center-grade AI accelerators; applications that need storage with latency that is lower than ~50 – 60 µs of modern high-end PCIe SSDs, though we will see how it compares to Z-NAND, and essentially a new generation of conventional 3D NAND with a new brand.
Except for the 400-layer-class Samsung BV-NAND that is set to hit the market in the foreseeable future, the company’s new tech, like zHBM and zNAND-O, is years away.
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