G.Skill explains how AMD EXPO ULL unlocks additional performance — expanded profiles allow memory makers to include subtiming tweaks for the first time
AMD’s EXPO Ultra Low Latency program, announced at Computex 2026, aims to give users a one-click route to lower memory latencies than its existing EXPO profiles, but the company’s initial announcement was light on details. To learn more about EXPO ULL, I stopped by G.Skill’s Computex booth, where the company demonstrated four new kits that offer EXPO ULL support.
Memory latency directly affects how long the CPU has to wait in order to get data back from RAM, and so it has a major impact on CPU performance. But even as new DDR standards and ever-faster DIMMs have boosted memory bandwidth, DDR latency has improved at a much slower pace over time.
For some very high-level background, when selecting memory, PC builders will generally consider a given memory kit’s speed and its CAS latency (CL). If you compare two CL30 memory kits, for example, the one with the higher clock rate will have a lower effective latency in nanoseconds (because CL30 expresses a number of clock cycles).
Knowing this, your first instinct for reducing latency might be to seek the highest-clocked memory you can find with the lowest CAS latency (like DDR5-8400 or even faster modules).
But on modern AMD platforms, it’s not that simple. Reaching memory speeds higher than 6000 MT/s generally requires the use of a 1:2 multiplier mode between the clock of the integrated memory controller (the UCLK), which generally tops out around 3000 MHz, and the memory clock (MCLK). This 1:2 multiplier adds latency, and so it can counterintuitively reduce performance even as memory speeds climb above 6000 MT/s. (Remember that DDR memory moves bits at twice the clock rate, hence MT/s).
With this 1:2 multiplier active, by the time additional memory clock speed even begins to bring latency back down to where it would generally be in the 1:1 mode, you’re looking at wildly expensive and exotic memory kits, and so most enthusiasts running Ryzen 7000 and Ryzen 9000 CPUs consider it desirable to choose memory that lets them run the UCLK and MCLK in 1:1 lockstep for the best balance of low latency and (relatively) low cost.
All that is why using memory faster than 6000 MT/s on AMD platforms is generally counterproductive for gaming performance. That’s why modules in the range of DDR5-6000 CL30 are widely regarded as the overclocking “sweet spot” for Ryzen 7000 and Ryzen 9000 CPUs.
But that doesn’t mean there isn’t further room for improvement, as the introduction of EXPO ULL suggests.
G.Skill told me that until now, DRAM module makers were only permitted to change the four primary timings within EXPO (and XMP) profiles, leaving performance on the table. EXPO ULL affords memory makers more freedom to adjust the sub-timings within each of those four primary timings for even lower latencies, and to include those results in the memory’s SPD.
Tweaking memory sub-timings on Ryzen platforms using community-made tools to determine the best potential settings used to be a fairly common practice for those seeking the best performance from their AMD systems, but Ryzen X3D processors and their massive slices of 3D V-Cache reduced those CPUs’ sensitivity to those finer adjustments. It’s become much more common to just get a DDR5-6000 CL30 kit, enable EXPO, and call it good.
But if you are focused on achieving the absolute lowest memory latency, EXPO ULL removes the need to perform the (tedious and tricky) process of determining those improved sub-timings by allowing memory makers to shoulder that work and include it as part of the one-click boost that EXPO provides.
For all that, EXPO ULL doesn’t change the fundamental performance characteristics of X3D versus non-X3D CPUs, so while you can certainly pair an X3D chip with an EXPO ULL kit, G.Skill tells me that you’re not going to see as large of a difference in performance from that pairing as you would with a non-X3D chip. That’s why AMD is touting the performance gains of EXPO ULL with a Ryzen 7 9700X and not the Ryzen 7 9850X3D you might expect.
G.Skill also told me that EXPO ULL-ready memory requires stricter binning of individual memory chips during production, so it isn’t just a software change that can be applied to existing modules. The company says the extra work involved in this stricter binning process means that modules supporting the feature are likely to be more expensive than kits that haven’t undergone the same characterization.
Overall, then, EXPO ULL is likely to be a premium (and somewhat niche) addition to the EXPO program instead of a broad replacement for non-ULL EXPO profiles. Demanding gamers who need the lowest memory latency for the best performance in CPU-bound gaming scenarios will likely want an EXPO ULL kit regardless of the type of Ryzen CPU they’re using. But we’ll have to see just how much extra cash these kits demand in today’s already eye-watering memory market and what benefit they have, if any, for AMD’s massively popular X3D chips.
