Qualcomm will license patents behind Huawei’s LogicFolding chip architecture, report says — the Kirin 9050 Pro already uses it, with a teardown showing its lower die is mostly cache and I/O
Qualcomm has reached a deal to license Huawei patents behind the LogicFolding chip-stacking method, Bloomberg reports. The technology, which is used in the Kirin 9050 Pro, splits nearly every block across two bonded dies, and a teardown and die shots show the lower die holds mostly cache and I/O.
Qualcomm’s multiyear, cross-license deal with Huawei has a wide scope, covering 5G devices, AI services, near- and co-packaged optics and networks, a Huawei spokesperson told Bloomberg. Qualcomm also intends to purchase specific Huawei U.S. patents in compute, AI, networking, and other technologies, according to a release. Neither company’s announcement named any patents, LogicFolding, or any chip that uses it.
Bloomberg’s report frames the deal as a win for Huawei, validating its chipmaking acumen. The deal remains subject to approval, and Qualcomm will reportedly pay Huawei to license its patents for the first time. According to the report, LogicFolding targets faster data transmission as a workaround for China’s lack of access to EUV lithography machines.
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The Kirin 9050 Pro is used in the Huawei Mate XT 2 tri-fold smartphone, launched Sept. 7. Geekerwan, a Chinese tech review channel known for in-depth chip testing, had a lab slice the chip for its teardown. Kurnal, a semiconductor researcher who publishes die-shot analysis, also posted annotated shots of both dies on X. Geekerwan’s cross-section shows the two dies bonded face to face, and both show the execution units on top, with the PLLs also on the lower die.
LogicFolding was first unveiled on May 25 by He Tingbo, president of Huawei’s semiconductor business, at IEEE ISCAS 2026 in Shanghai, under the company’s “Tau Scaling Law,” which uses signal delay rather than transistor size as a measure. Huawei describes both layers as active and working as one. Vertical interconnects work to create shorter signal paths, which can reduce energy consumption. Peking University’s “true 3D” design tool for the technology shows a 30% wire-length cut in its own tests.
Huawei’s papers describe a “Kirin 2026” chip whose figures match the Kirin 9050 Pro’s. In a paper last month, relayed by TrendForce, Huawei said the chip uses a 1.5-micrometer hybrid-bonding pitch with about 50 million interconnects. About 10–15% of those carry signals. Core routing is 20% shorter, with critical paths up to 70% shorter. Power is reduced by as much as 66% for NPU, 58% for GPU, and 41% for a CPU performance core at the same performance level. NPU performance holds 29 TOPS at 63% less frequency and at a lower voltage.
Huawei does not name a process node. On its roadmap is Kirin 2027 at a 1-micrometer pitch and more than 100 million interconnects; for around three years out, a 720-nanometer pitch with over 200 million. It is targeting a 1.4nm-class density by 2031, with LogicFolding in the Ascend 990 AI accelerator around 2030. HiSilicon, Huawei’s chip-design unit, designs the Kirin chips, and SMIC is believed to make them, according to Reuters via TrendForce. It isn’t stated who handles the bonding process.
As for the Kirin 9050 Pro, Geekerwan tested it in a Mate 90 Pro Max phone. Analysis shows that the two dies are bonded with copper-to-copper hybrid bonding, metal layer to metal layer. The bonded circuit layers of both dies sit between two thick layers of silicon rather than directly on the package substrate. For the interconnects, about 80,000 through-silicon vias (TSVs) run through the lower die, taking up, with their keep-out zones, about 8% of the lower die’s usable area, Geekerwan says.
The split spans both dies. In the big CPU core, the execution units are on top, with the L1 and L2 caches directly beneath the load/store units, Geekerwan says. Kurnal’s die shots put the GPU and NPU logic over their caches too. The lower die also holds a shared L3, a 12MiB system cache, PLLs, and the LPDDR, PCIe, camera, display, UFS, and USB interfaces, while the top die carries the ISP, modem, and memory controllers. Cache, I/O, and PLLs produce less heat and are less sensitive to the process, so they go below, Geekerwan explains; the denser compute goes on top, on a somewhat more advanced process.
Each die is just over 120 mm², which is smaller than the previous chip’s 140-plus mm². The total silicon area for both is therefore over 240 mm², up 70% overall. Density rose from 155 to 238 MTr/mm² at launch, about 53.5% higher, according to Huawei’s launch numbers. Other notable changes include the NPU’s area, up 150% across both dies, with Geekerwan measuring 68 TOPS INT8. The configuration makes sense and the rationale follows the layout, but an independent die analysis is needed for full understanding.
Huawei’s stacking approach has its competitors. TSMC’s SoIC roadmap set a 6-micrometer bond pitch for 2025 and 4.5 micrometers by 2029, with 3nm chip stacking in volume production last year. Intel’s Foveros Direct is said to have “copper bonding at a pitch of 9µm,” which reached high volume with the Clearwater Forest Xeon, and a second generation targets 3 micrometers. AMD’s first-generation 3D V-Cache stacks a 64MB L3 SRAM die on a complete CPU die, using direct copper bonding at a 9-micrometer pitch. Huawei’s 1.5-micrometer claim comes from its own paper and any comparison has to be taken with a grain of salt.
As to why Qualcomm might be interested, John Han, executive vice president and general manager of Qualcomm Technology Licensing, said the agreement reflects Qualcomm’s “recognition of Huawei’s continued innovation and intellectual property in 5G and other technology fields.” Bloomberg’s report says that at least some of the patents underpin LogicFolding, but no source names the patents. Dr. Ian Cutress, chief analyst at More Than Moore, questioned how new Huawei’s Tau Scaling is, writing on X that it is “a repackaging of what the industry has always done.”
Upon “receipt of the necessary regulatory approvals,” the cross-license and patent purchase deal should proceed. The deal is also subject to Federal Trade Commission review under the Hart-Scott-Rodino Act, Bloomberg reported. That U.S. premerger law sets a minimum deal size, $133.9 million this year, among other tests, and the deal’s value wasn’t disclosed.
Nikkei Asia reported that Qualcomm will be the net payer under the deal; Qualcomm’s licensing revenue stopped including Huawei royalties in fiscal Q2 2025, after the license expired. This follows a long history of Huawei paying for Qualcomm licenses, an agreement first inked in 2001. Huawei says it has brought in more license-related income than it’s spent since 2021. Patents behind its chip-stacking method reportedly join that business under the deal.
The industry now waits to see what comes of the FTC review. Qualcomm’s fiscal Q4 results should come early next month, as last year’s did, but its fiscal year ended Sept. 27, before the deal was announced. Additional independent analysis of the 9050 Pro’s die may come from TechInsights or SemiAnalysis. Also of interest is the next iteration in Huawei’s Kirin 2027, to see if its claims are met. The deal between the two companies currently lacks details on the extent of patent coverage, but the silicon on record can help reveal the nature of Qualcomm’s interest.
