OpenAI’s Jalapeño ASIC is a seismic shift for the industry, not because of its efficiency or performance, but because of how it was designed. The company was clear from the jump that AI played a big role in the design process of Jalapeño, not only for the hardware itself, but also in the co-design with OpenAI’s software stack, allowing the ASIC to go from initial register-transfer level (RTL) to tapeout in a matter of just nine months. From concept to reveal, the timeline was less than two years. Richard Ho, head of hardware at OpenAI, says the timeline “established a new baseline,” and that the industry is already knocking on OpenAI’s door to learn how the company pulled it off.
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(Image credit: Microsoft)
“The way I like to think about it is, we’ve established a new baseline. In the old baseline, you’re talking 18 months to two years, roughly. Often that’s even with some existing IP or some more legacy architecture design,” Ho told Tom’s Hardware Premium in an interview. “We’re starting from scratch here. We had nothing. There’s not a line of code here to refer to. What we’ve established is that there’s a new baseline that you can do with a very talented team with the help of AI. Now, does it get shorter? It depends on what you’re trying to do.”
AI usage in chip design is nothing new, predating the era of LLMs entirely. The largest Electronic Design Automation (EDA) companies, Cadence and Synopsys, have a portfolio of AI-assisted chip design tools that have been around for several years. The models OpenAI used were its own internal models, however, and it leveraged both existing EDA tools and its new AI-assisted engineering workflow.
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The engineering team used OpenAI’s agentic coding platform, Codex, for the Jalapeño design. “But we think that every engineering team in chip design should be able to use this as a new baseline, because it’s a proof point that the models that are in use — the AI models for us is mostly Codex, Sol, the one before Sol, and now we’re moving on to Astra. These are super capable. Even from when we started that work, back in November 2025, to when we taped out, the models improved enormously. Even from that moment to when we started doing the kernel optimization in May, when the chips were first coming online, we ourselves were shocked at how much better Codex was and what it could do,” Ho said.
A free PCB viewer from Cadence Design. (Image credit: Cadence)
Although AI was used during the entire development process, not only for design itself but also in writing and optimizing kernels, Ho continually reiterated the importance of talented engineers guiding those systems. The development story of Jalapeño is one of the few clear examples of AI bolstering a team of human workers, not displacing them.
Ho described the development cycle as a “good model” of how engineering teams should operate in the AI era. “This is how AI should be used. We didn’t replace our engineers; they just became super productive. With a smaller team of really good engineers with a lot of this AI stuff, you could do things faster and better than you could otherwise. I think that’s a good model of how engineering should be approached in the AI age.”
Although OpenAI managed to get working silicon much faster than a traditional development cycle, it wasn’t free of issues. For starters, OpenAI’s B0 stepping of Jalapeño reportedly delivers up to a 25% improvement in performance per watt over the original A0 stepping. That’s closer to a generational improvement than stepping optimization, suggesting that, at least for a brand new hardware team, there may have been design oversights with the original stepping. Attributing that to AI or humans is anyone’s guess.
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Other frontier labs are circling for a slice of the pie, as well. Clive Chan, a key engineer on Jalapeño and the second-ever hardware hire at OpenAI, left the company in June to join the hardware team at Anthropic. Ho says there’s already been “a lot of interest in the industry” for OpenAI’s AI-assisted chip design process, and says that “we’ll see more about that quite shortly.”
“I’m not going to preempt anything here. I can tell you that there’s a lot of interest in the industry, and I would also tell you that we feel that there is a lot of benefit in industry generally that we want to enable,” Ho said. “I think that’s something that we’ll see more about quite shortly, to be honest.”
Ho referenced the dozens of AI-first chip design startups in Silicon Valley, suggesting OpenAI may eventually introduce tools of its own to aid other firms with AI chip development. “We have our take on that, and I think at some point we want to tell the world, “Here’s our take on it.” Fundamental to that is Codex and GPT-6 Astra coming out. Those are fundamental, and we can basically point to it; it’s not going to be slideware or vaporware. We can point to it and say, “Here’s what we did, here’s how we did it, and here’s what we got.” It’s going to be very concrete.”
(Image credit: OpenAI)
What exactly the “it” Ho is referring to here remains a mystery, though given the context, it sounds like OpenAI may explore some way to productize its AI chip design workflow. Ho says Astra is a big step toward that, and we’ve already seen the model in action performing impressive feats, such as completing Portal autonomously.
Although OpenAI leveraged its own models heavily for Jalapeño’s design and validation, it didn’t completely break the mold of traditional EDA workflows, particularly at the end of the design process. Before tapeout, tools from companies like Synopsys and Cadence perform a series of tests for signoff, including static timing analysis and signal integrity analysis. Ho says that OpenAI used this typical EDA flow for Jalapeño.
“But for sign-off, you need to use the standard EDA flows, and we did, because you want to make sure those results are good and correct. There’s no real alternative today. Part of it is this combination of standard flows optimized with AI, optimized by really good engineers,” Ho said.
OpenAI shared a multi-generational roadmap for accelerators. It says its second-gen ASIC is approaching tape-out, and its third generation is already in development. Although Ho said that the Jalapeño development cycle establishes a new baseline for chip design timelines, he was cautious about calling that cycle and cadence.
“Our projects and tape-outs will be dependent on the maturity level of the technologies. We can do very fast execution. Will we do those types of executions back-to-back? I doubt it, because the technology will not be ready for that, and I don’t want to tape out something that is 2% better than what I taped out before, because it’s not worth it to change a fleet,” Ho told us.
The executive was also clear that the Jalapeño timeline isn’t necessarily the same timeline all chips will follow. There were some “pragmatic trade-offs” in the early architecture design, with the team avoiding emerging, complex design points like 3D stacking and co-packaged optics. “Will it take longer? Will it take nine months? I won’t say it will take nine months… but I think it will go faster than if you didn’t have AI models.”
You can read the full transcript of the interview, which covers a wide range of topics, at Tom’s Hardware Premium.
