AMD used its recent Advancing AI 2026 event in San Francisco to launch sixth-gen EPYC “Venice” processors, Instinct MI400 Series GPUs, and Helios rack-scale systems, and to confirm that the Zen 7 generation arriving in 2028 will launch as three separate EPYC families rather than one.
The company named Florence, Ferrara, and Fidenza in its launch release, extended its annual CPU, GPU, networking, and rack cadence out to 2030, and put its total addressable market at roughly $2 trillion in 2030. It also introduced a competitive yardstick it hasn’t used before, claiming the most AI agents per watt, per dollar, and per rack, though its own endnotes state those agent counts are estimated from CPU thread resources used as a proxy.
Three Zen 7 CPUs
Florence carries fresh Zen 7 cores, a new set of AI compute extensions, and support for newer memory technologies, AMD chair and CEO Lisa Su said during the keynote. Ferrara is the AI host node portion, and it appears a second time further along the roadmap as the CPU inside the Helios 600 rack alongside MI600 Series GPUs and Pensando “Palma” and “Levanzo” networking. Fidenza, meanwhile, is the agentic sandbox product. AMD disclosed no core counts, no process node, and no socket for any of the three, and said only that Zen 7 uses leading-edge process technology.
Latest Videos FromTom’s Hardware
The fourth-gen EPYC generation, built on Zen 4, spanned Genoa, Bergamo, Genoa-X, and Siena across two sockets. The fifth-gen “Turin” generation then went the other way, folding Zen 5 and Zen 5c parts into a single 27-SKU stack on one socket with no separate cache-stacked or edge line at launch. Venice restarts the fan-out, with the 9006 series on the new SP7 socket now, and Venice-X arriving in 2027 with 1,152MB of 3D V-Cache, 96 cores, and a 5.15 GHz boost clock. Three named Zen 7 families at announcement, two years out, is a wider spread than AMD has ever opened a generation with.
AMD’s own portfolio endnote describes the EPYC range as covering general-purpose enterprise, cloud, telecom, SMB, and HPC systems, plus, as a distinct category, sandboxed agentic AI deployments and GPU head node servers. Su told analysts in May that AMD was already working with customers on architectures beyond Venice, without naming categories at the time. The Zen 7 lineup puts a name to those two AI-specific segments for the first time.
Agents per rack
AMD’s main server CPU claim at the event is that sixth-gen EPYC enables the most agents per watt, per dollar, and per rack. Endnote 9xx6-012 in the launch release states that agent counts are estimates derived from available CPU thread resources used as a proxy under a consistent theoretical workload, and that real capacity varies with workload, model, memory, software, orchestration, and system configuration. The per-rack comparison behind it is core count at a 100 kW rack power envelope, pitting the 256-core EPYC 9996 against an 88-core Nvidia Vera, AMD’s own 192-core EPYC 9965, and Intel’s 128-core Xeon 6980P. The per-dollar metric is based on top-of-stack thread count divided by the 1,000-unit list pricing.
The per-watt comparison in that endnote lists Nvidia Vera at 450W and Arm’s AGI CPU at 300W with one thread per core, alongside Intel’s Xeon 6980P at 500W and AMD’s EPYC 9965 at 500W. AMD had already claimed a 3.3 times rack-level advantage over Vera in June. Mercury Research put AMD at a record 46.2% of x86 server CPU revenue in Q1 2026, against 33.2% of units, and Arm-based designs took roughly 17.7% of server shipments in the same quarter, so the widening comparison shows where these units are going.
Starting with sixth-gen EPYC, AMD has replaced TDP with a figure it calls Default CPU Power, defined as total power consumed across the processor’s compute and I/O dies at a stated performance target. AMD says both references can serve for product comparison and performance-per-watt analysis, and the endnote itself mixes the two conventions, quoting the EPYC 9956 at 400W Default CPU Power against TDP figures for the Nvidia, Intel, and Arm parts.
2030 cadence
Helios racks pair 72 Instinct MI455X GPUs with 18 Venice CPUs, 31TB of HBM4, and 1.4 PB/s of aggregate memory bandwidth, and are in production now. AMD claims up to 30% more inference tokens per dollar than Nvidia’s Vera Rubin NVL72, based on AMD Performance Labs estimates from July 2026 using a Kimi K2 Thinking workload at 32K input and 8K output, with hourly GPU pricing projections. The 34-times token throughput gain AMD quotes for MI455X over MI355X comes from AMD’s own measurements on DeepSeek V4 Flash at FP4. Both, however, are vendor-provided benchmarks with no independent verification yet.
The forward roadmap runs MI500 Series GPUs in 2027 inside a Helios 500 rack built on EPYC “Verano” and Pensando “Como” and “Monza” networking, MI600 Series in 2028 inside Helios 600 on Ferrara, and Ravenna on Zen 8 in 2030.
OpenAI expects to bring Helios online from the fourth quarter of 2026, with deployments accelerating through 2027, while Meta is validating sixth-gen EPYC platforms in its labs and has begun testing Helios racks. Anthropic committed the day before the keynote to up to 2GW of MI455X GPUs in Helios systems, with the first gigawatt due in the first half of 2027. SemiAnalysis reported in February that manufacturing delays would push mass production and first production tokens on an MI455X UALoE72 system to Q2 2027; AMD software chief Anush Elangovan publicly rejected that assessment and said Helios remained on target for 2H 2026.
AMD’s cautionary statement in the launch release lists the availability of essential components, naming memory supply specifically, among the risk factors that could cause results to differ from its projections. A Helios rack carries 31 TB of HBM4, and DRAM contract prices roughly doubled quarter-on-quarter in Q1 2026 before rising again in Q2.
